Turbo coding is used as a channel coding scheme for high-speed data transmission in mobile communication systems, such as a third generation Wideband Code Division Multiple Access (WCDMA) system and fourth generation Long-Term Evolution (LTE) or Worldwide Interoperability for Microwave Access (WiMax) 16 m systems.
Turbo coding is regarded as an important enhancement to Forward Error Correction (FEC). Although there are various types of turbo coding, representative types thereof use multiple encoding stages separated by interleaving steps in combination with iterative decoding. Such a combination of multiple encoding stages and iterative decoding provides communication systems with a higher noise limit in comparison to other existing FEC schemes. That is, turbo coding enables reliable communication with lower energy per bit relative to the noise power spectral density in comparison to other existing FEC schemes.
FIG. 1 is a block diagram of a turbo decoder. A turbo decoder core 100, which is commonly used for traffic processing in a modern mobile communication system based on WCDMA, LTE or WiMax 16 m, is basically composed of two or more component decoders.
In the example shown in FIG. 1, a decoding process of the turbo decoder core 100, one component decoder takes channel inputs and log-likelihood ratio (LLR) values produced by the other component decoder as input and produces new LLR values as output. The new LLR values can be used by the other component decoder as additional LLR values together with a received input signal to thereby produce more accurate LLR values.
More specifically, LLR soft inputs are interleaved through the first interleaver 130 and are fed to the first component decoder 110, and the output from the first component decoder 110 is de-interleaved through the de-interleaver 140. The de-interleaved signal is fed to the second component decoder 120 and is decoded. The decoded signal is interleaved through the second interleaver 150 and is fed back to the first component decoder 110. That is, the signal is processed through an iterative structure, wherein the output of the first component decoder 110 is fed to the second component decoder 120 and the output of the second component decoder 120 is fed back to the first component decoder 110.
The turbo decoder core 100 can produce highly accurate LLR values through iterative decoding. The turbo decoder core 100 performs iterative decoding until a given number of iterations is reached and then makes a hard decision on final soft outputs to produce the decoded values. In a turbo decoder core 100 having two or more component decoders, the component decoders exchange LLR values with each other during iterative decoding and produce more accurate LLR values with increasing number of iterations, gradually enhancing error correction capabilities.
Meanwhile, the throughput obtainable by using only one decoder core may be insufficient for high performance. Hence, a high-speed data system such as the LTE system may use a multi-core decoder having multiple decoder cores.
FIG. 2 is a block diagram of a multi-core turbo decoder. The multi-core decoder 200 includes two or more decoder cores 220, 230, 240 and 250. LLR data of the LLR memory 280, as an FEC block, is fed through Hybrid-ARQ (HARQ) combining 290 to the multi-core decoder 200. The controller 210 of the decoder 200 feeds LLR data to idle decoder cores 220, 230, 240 and 250 in sequence. That is, initially, LLR data is sequentially input to the decoder cores 220, 230, 240 and 250. Thereafter, when all the decoder cores 220, 230, 240 and 250 are involved in decoding LLR data, the controller 210 selects one decoder core that has completed decoding of assigned LLR data and feds the next FEC packet to the selected decoder core.
In the turbo decoder 200 having an existing multi-core configuration, LLR data as an FEC block is assigned to one decoder core selected in sequence without consideration of processing conditions. As such, when the FEC block size varies widely, a particular decoder core may be heavily loaded unless input FEC blocks are rearranged according to their sizes. This may increase the decoding time and reduce decoding throughput.
In addition, decoding throughput reduction can increase differences between output times of related FEC blocks during multi-user information processing. This may require an increase in the size of the output memory 270 for FEC block rearrangement, increasing hardware complexity.